The majority of present day integrated circuits (ICs) are implemented by using a plurality of interconnected field effect transistors (FETs), which may be realized as metal oxide semiconductor field effect transistors (MOSFETs or MOS transistors). A MOS transistor may be realized as a p-type device (i.e., a PMOS transistor) or an n-type device (i.e., an NMOS transistor). Moreover, a semiconductor device can include both PMOS and NMOS transistors, and such a device is commonly referred to as a complementary MOS or CMOS device. A MOS transistor includes a gate electrode as a control electrode that is formed over a semiconductor substrate, and spaced-apart source and drain regions formed within the semiconductor substrate and between which a current can flow. The source and drain regions are typically accessed via respective conductive contacts formed on the source and drain regions. Bias voltages applied to the gate electrode, the source contact, and the drain contact control the flow of current through a channel in the semiconductor substrate between the source and drain regions beneath the gate electrode. Conductive metal interconnects (plugs) formed in an insulating layer are typically used to deliver bias voltages to the gate, source, and drain contacts.
Strain engineering is often used to enhance the performance of semiconductor transistor devices. For example, embedded strain elements (i.e., doped or undoped semiconductor material that laterally stresses the channel region) can be used to improve the mobility of carriers in the channel region. Other approaches, such as the stress memory technique (SMT) and the use of tensile plasma enhanced nitride (TPEN) as a stress liner can be used to impart stress to a semiconductor transistor device. These approaches, however, indirectly apply stress to the channel region. Consequently, these techniques result in somewhat inefficient coupling of stress to the channel region.
Accordingly, it is desirable to efficiently apply stress to the channel region of a semiconductor transistor device in a way that does not require complex process steps. In addition, it is desirable to have a semiconductor device substrate that includes semiconductor material with a stressed region suitable for fabricating the channel region of a semiconductor transistor device. Furthermore, other desirable features and characteristics will become apparent from the subsequent detailed description and the appended claims, taken in conjunction with the accompanying drawings and the foregoing technical field and background.